
IPmux-2L
TDM Pseudowire Gatewa
Preserves investment
in legacy equipment in
migration to PSN
High-performance ASIC-based buffering
and forwarding techniques achieve
minimal end-to-end processing delay.
Configurable packet size balances PSN
throughput and delay, while a jitter buffer
compensates for packet delay variation
(jitter) of up to 200 msec in the network.
An assigned, IANA-registered UDP port
number for pseudowire simplifies flow
classification through switches and
routers.
CLOCKING
Synchronization between TDM devices is
maintained by deploying advanced clock
distribution mechanisms. The clocking
options are:
Internal – The IPmux-2L internal clock
oscillator provides the master clock
source for the TDM circuit
Loopback – The transmit clock is
derived from the TDM or serial data
receive clock
Adaptive – The clock is recovered from
the PSN
Receive – The system timing is locked
to the clock received via one of the
TDM ports or the third FE port (Sync-E
option).
The system clock ensures a single clock
source for all TDM links and uses master
and fallback timing sources for clock
redundancy. The system timing also
supports two different clock sources from
two TDM links at the same time.
TIMING OVER PACKET
IPmux-2L utilizes standard Synchronous
Ethernet (Sync-E) technology to ensure
highly accurate clock recovery over PSN
(special ordering option). The clock
operation conforms to ITU-T G.8261
requirements.
PSEUDOWIRE QoS
IPmux-2L performs VLAN tagging and
priority labeling according to 802.1p&Q.
Pseudowire packets are assigned a
dedicated VLAN ID and 802.1p bit.
The ToS or Diffserv of the outgoing
pseudowire packets are user-configurable.
This allows assigning pseudowire packets
a higher priority in IP networks.
EXP bits are used for QoS marking of the
TDMoMPLS traffic in MPLS networks.
Figure 1. LAN and TDM Services over a Wireless Ethernet Link
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